XE-LM (Logic Modeling) is verilog logic modeling generation tool for ATPG and LEC.

XE LM Diagram

              • Transform a transistor-level design into a logical model with generic primitives.
              • Preserve as many nodes in the original schematic netlist as possible.
              • Preserve the hierarchy in the original schematic netlist.Allow user to supply a verilog model for a particular sub-circuit.Allow user to modify the hierarchy in the original schematic netlist:
                • Flatten a sub-circuit
                • Move transistors or an entire sub-circuit into another sub-circuit
                • Delete transistors or an entire sub-circuit.

Following is an example of XE-LM verilog modeling generation on senseamp-flop: